1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a liquid crystal display and a driving method thereof for preventing a gate driver from generating an abnormal output.
2. Description of the Related Art
Generally, liquid crystal displays (hereinafter, referred to as LCD) are used as the monitors of computer notebooks to control the light transmittance of liquid crystals using an electric field, thereby displaying pictures corresponding to video signals. Such an LCD, as shown in FIG. 1, includes a liquid crystal display panel 1 where liquid crystal cells are arranged in a matrix and a drive circuit to drive the liquid crystal display panel. The liquid crystal display panel 1 includes a thin film transistor MN (hereinafter, referred to as TFT MN) formed adjacent each intersection of gate lines GL1 and GL2, and data lines DL1 and DL2 to switch a signal voltage that is supplied to a liquid crystal cell Clc to control the light transmittance of a liquid crystal cell Clc in accordance with the voltage level of each video signal. In response to a gate signal from the gate line, the TFT MN supplies the video signal from the data line to the liquid crystal cell Clc. The liquid crystal cell Clc includes a common electrode and a pixel electrode (not shown), which face each other with liquid crystals therebetween. The pixel electrode (not shown) is connected to the TFT MN. The pixel electrode is formed at a cell area defined by the gate line and data line, which cross each other perpendicularly.
The drive circuit includes a gate diver 3 to drive the gate lines on the liquid crystal display panel, a data driver 15 to drive the data lines on the liquid crystal display panel 1, and a timing controller 9. The timing controller 9 supplies a timing control signal to the gate driver 3 and the data driver 5 to control them and, in addition, supplies a pixel data to the data driver 5. Further, the drive circuit includes a power supply 11 to supply a power supply voltage for driving the whole system, and a masking part 7 to mask a gate output enable signal (hereinafter, referred to as GOE) that is one of control signals to be applied to the gate driver 3.
The data driver 5 inputs a data control signal, such as a data clock, etc., together with red R, green G and blue B data signals from the timing controller 9. The data driver 5 acts to apply pixel signals corresponding to the pixel data of one line to the data line whenever the gate signal (or a scan signal) from the gate driver is applied to the gate line. The gate driver 3 sequentially applies the gate signal to the gate lines to sequentially drive the gate lines for each horizontal synchronization signal period. In other words, the gate driver 3 acts to generate the gate signal (or the scan signal) that sequentially selects the gate line. A gate high voltage is applied to each gate line only for the corresponding vertical synchronization period, and a gate low voltage is applied to each gate line for the remaining period. The video data on the data line is supplied to the pixel electrode of the liquid crystal cell Clc through the TFT MN in response to the gate signal (or scan signal) input from the gate driver 3.
The timing controller 9 controls the drive timing of the gate driver 3 and the data driver 5 in response to horizontal and vertical synchronization signals and a data clock input from an external source, such as a graphic card within a computer system. The timing controller 9 generates the control signals for the gate driver 3 and the data driver 5, including a gate output enable signal GOE and a data output enable signal, using the data clock, the horizontal and vertical synchronization signals. Further, the timing controller 9 supplies an input video data signal R, G and B from an external source to the data driver 5.
The power supply part 11 supplies a power supply voltage to each circuit part for driving the whole system. The masking part 7 selectively masks the gate output enable signal GOE that designates an output point in time of the gate driver 3 in accordance with the logic state of a reset signal. FIG. 2 is a diagram illustrating a detailed configuration of a masking part in FIG. 1. FIG. 3 is a waveform diagram of input and output signals of the masking part of FIG. 2. The masking part shown in FIG. 2 will be explained in conjunction with the waveforms shown in FIG. 3.
Referring to FIG. 2, the masking part 7 includes a first D flip-flop 21a (hereinafter, referred to as F/F) to a sixth D F/F 21f receiving a vertical synchronization signal BVSY at their clock terminal CLK through a first inverter 23a from a synchronization signal input terminal 17, and an AND-gate 25 to perform a logical product operation on a reset signal RESET from a reset input terminal 19 and an output signal of the first D F/F 21a. Further, the masking part 7 includes an OR-gate 27 to switch the gate output enable signal GOE from the timing controller 9 in accordance with the output signals from second and third inverters 23b and 23c. 
Each of the D F/F's 21a–f latches the input signal at its input terminal D to its output terminal Q at the point in time when the inverted vertical synchronization signal from the first inverter 23a, which is supplied to its clock terminal CLK, is changed from low state to high state, that is as at the rising edge of the inverted vertical synchronization signal BVSY Further, each D F/F 21 receives the power supply voltage Vcc at its preset input terminal PR. In addition, each D F/F 21 receives the reset signal RESET at its clear terminal CLR. While the reset signal RESET is in a low logic state, each D F/F 21 initializes the output terminal Q and the inversion output terminal Q. A signal coming out from the inversion output terminal Q has an opposite polarity to the output signal from an output terminal Q.
As further shown in FIG. 3, the power supply voltage Vcc and the reset signal RESET remain at a normal voltage since power is supplied. The first D F/F 21a receives the reset signal RESET from the reset input terminal 19 at its input terminal D, and inversely receives the vertical synchronization signal BVSY from the synchronization signal input terminal 17 at the clock terminal CLK through the first inverter 23a. Further, the first D F/F 21a latches the reset signal RESET input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is first changed from low state to high state, that is at the rising edge of the inverted vertical synchronization signal BVSY Accordingly, the first D F/F 21 Aadelays the reset signal RESET for a period corresponding to one vertical synchronization signal.
The AND gate 25 shown in FIG. 2 is connected between the output terminal Q of the first D F/F 21a and the input terminal D of the second D F/F 21b, and performs a logical product operation on the reset signal RESET first-delayed at the output terminal Q of the first D F/F 21a and the reset signal RESET input from the reset input terminal 19. Further, the AND-gate 25 ensures that the signal output at the output terminal Q of the first D F/F 21a is input to the input terminal D of the second D F/F 21b. However, it is indifferent to the presence or absence of the AND-gate 25.
The second D F/F 21b receives the output signal, on which logical product operation is performed by the AND-gate 25, at its input terminal D and the inverted vertical synchronization signal BVSY at the clock terminal CLK through the first inverter 23a. The signal coming out at the output terminal Q of the second D F/F 21b is input to the data input terminal D of the third D F/F 21c. And, the second D F/F 21b latches the first-delayed signal input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is changed from low state to high state, that is, at the rising edge of the inverted vertical synchronization signal BVSY Accordingly, the second D F/F 21b delays the first-delayed reset signal RESET again for a period corresponding to one vertical synchronization signal. In other words, the second D F/F 21b second delays the reset signal RESET.
The third D F/F 21c receives the reset signal RESET second-delayed at the output terminal Q of the second D F/F 21b, at its input terminal D. Further, the third D F/F 21c supplies the signal coming out at its output terminal Q to the data input terminal D of the fourth D F/F 21d. And, the third D F/F 21c latches the second-delayed signal input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is changed from low state to high state, that is, at the rising edge of the inverted vertical synchronization signal BVSY. Accordingly, the third D F/F 21c delays the second-delayed reset signal RESET, which is delayed by the first D F/F 21a and the second D F/F 21b, again for a period corresponding to one vertical synchronization signal. In other words, the third D F/F 21c third delays the reset signal RESET.
The fourth D F/F 21d receives the reset signal RESET third-delayed at the output terminal Q of the third D F/F 21c, at its input terminal D. Further, the fourth D F/F 21d supplies the signal coming out at its output terminal Q to the data input terminal D of the fifth D F/F 21E. And, the fourth D F/F 21d latches the third-delayed signal input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is changed from low state to high state, that is, at the rising edge of the inverted vertical synchronization signal BVSY. Accordingly, the fourth D F/F 21d delays the third-delayed reset signal RESET, which is delayed by the first D F/F 21a to the third D F/F 21c, again for a period corresponding to one vertical synchronization signal. In other words, the fourth D F/F 21d fourth delays the reset signal RESET.
The fifth D F/F 21e receives the reset signal RESET fourth-delayed at the output terminal Q of the fourth D F/F 21d, at its input terminal D. Further, the fifth D F/F 21e supplies the signal coming out at its output terminal Q to the data input terminal D of the sixth D F/F 21f. And, the fifth D F/F 21e latches the fourth-delayed signal input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is changed from low state to high state, that is, at the rising edge of the inverted vertical synchronization signal BVSY. Accordingly, the fifth D F/F 21e delays the fourth-delayed reset signal RESET, which is delayed by the first D F/F 21a to the fourth D F/F 21d, again for a period corresponding to one vertical synchronization signal. In other words, the fifth D F/F 21e fifth delays the reset signal RESET.
The sixth D F/F 21f receives the reset signal RESET fifth-delayed at the output terminal Q of the fifth D F/F 21e, at its input terminal D. Further, the sixth D F/F 21f supplies the signal coming out at its output terminal Q to the second inverter 23B. And, the sixth D F/F 21f latches the fifth-delayed signal input at its input terminal D to its output terminal Q at the point in time when the vertical synchronization signal BVSY inversely input at the clock terminal CLK is changed from low state to high state, that is, at the rising edge of the inverted vertical synchronization signal BVSY. Accordingly, the sixth D F/F 21f delays the fifth-delayed reset signal RESET, which is delayed by the first D F/F 21a to the fifth D F/F 21e, again for a period corresponding to one vertical synchronization signal. In other words, the sixth D F/F 21f sixth delays the reset signal RESET.
The second inverter 23b inverts the output signal delayed through the output terminal Q of the sixth D F/F 21f, and the inverted reset signal RESET is applied to the OR-gate 27. The OR-gate 27 performs logical sum operation on the output signals of second and third inverters 23b and 23c and a gate output enable input signal GOE_IN from the timing controller 29. In other words, the OR-gate 27 switches the gate output enable input signal GOE_IN in accordance with the logical state of the reset signal RESET delayed and inverted by each of the D F/F's 21 and the second inverter 23b and the reset signal RESET inverted by the third inverter 23c. As shown in FIG. 3, the gate enable signal is intercepted for the period of six vertical synchronization signals from the point in time when the reset signal is changed from low state to high state by the OR-gate 27.
As a result, the masking part, as shown in FIG. 3, further intercepts the gate output enable signal GOE for a period corresponding to the six vertical synchronization signal from the point in time when the reset signal is changed from low state to high state as well as for a period when the reset signal RESET remains at a low state. Thus, the masking part of the related art LCD masks the gate output enable signal GOE for a designated vertical synchronization period when the power source is applied, thereby preventing an overcurrent, which is generated at the near point in time when the power is applied, from being supplied. However, the gate high voltage (hereinafter referred to as Vgh) can have a voltage level lower than a specified voltage level due to the un-stability of power supply while the gate driver 3 is driven normally. When the gate high voltage Vgh is in an abnormal state, the overcurrent can flow into the circuit device of the gate driver 3 and the liquid crystal display panel 1 and the circuit device of the data driver 5. Such an overcurrent may cause a damage on the gate driver 5, the liquid crystal display panel 1 and the data driver 3.